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title

Online Fault-Tolerant Mechanism for link errors in 2-D Mesh Network-On-Chip based on HDL implementation

Credit to Download: 1 | Page Numbers 12 | Abstract Views: 85
Year: 2016
COI code: ELEMECHCONF04_406
Paper Language: English

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Authors Online Fault-Tolerant Mechanism for link errors in 2-D Mesh Network-On-Chip based on HDL implementation

  Rashid Hatami - Faculty of Information, Communication and Security Technology Malek Ashtar University of Technology
  Pejman Shahhosseini - Faculty of Electrical Engineering Malek Ashtar University of Technology
  Mohammad Amin Amiri - Faculty of Electrical Engineering Malek Ashtar University of Technology

Abstract:

This paper presents an efficient method for online fault detection and correction in Network-on-Chip switches, named Misdirection Correction Code. The proposed method deals with link errors that occur during the traversal of flits caused by channel disturbances such as stuck at, cross-talk, coupling noise, and transient faults. When the transmission path is breakdown due to any faults induced, first the address fault is detected and corrected and then the corrected address is transmitted through links between the switches. The proposed method decreases the transmission time delay and ensures effective communications in Network-on-Chip. To evaluate the effectiveness of the proposed fault tolerant approach a VHDL-based fault injection method is presented. A VHDL model for Network-on-Chip switch is developed. The Modelsim simulation Tool is used as simulation tool and QuartusⅡ is utilized to synthesize the VHDL model of Network-on-Chip switch with fault detection and correction mechanism. The experiment results show that the proposed method has lower overhead, lower delay and higher fault coverage in comparison with the existing method for detection and correction of faults in Network-on-Chip

Keywords:

Network-on-Chip, Online Fault Correction, Link Errors

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COI code: ELEMECHCONF04_406

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Hatami, Rashid; Pejman Shahhosseini & Mohammad Amin Amiri, 2016, Online Fault-Tolerant Mechanism for link errors in 2-D Mesh Network-On-Chip based on HDL implementation, 4th  national conference on applied research in electrical, mechanical and mechatronic, تهران, دانشگاه صنعتي مالك اشتر, https://www.civilica.com/Paper-ELEMECHCONF04-ELEMECHCONF04_406.htmlInside the text, wherever referred to or an achievement of this article is mentioned, after mentioning the article, inside the parental, the following specifications are written.
First Time: (Hatami, Rashid; Pejman Shahhosseini & Mohammad Amin Amiri, 2016)
Second and more: (Hatami; Shahhosseini & Amiri, 2016)
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Scientometrics

The University/Research Center Information:
Type: state university
Paper No.: 6588
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