A Fault-Tolerant Approach to Embedded-System Design Using Software Standby Sparing

A fault-tolerant approach for application-specific instruction-set processor (ASIP) to reduce the cost of classical fault-tolerant mechanisms is presented in this paper. The ASIP is synthesized from an object-oriented high-level description by a hardwaresoftware co-design approach and consists of a processor core along with some functional units. In the proposed fault-tolerant methodology, upon detecting a fault in a hardware functional unit, this unit is replaced by an equivalent software version. To evaluate the fault-tolerant approach, a JPEG processor is used. The analytical and experimental results show that the approach can tolerate functional-unit faults with no area/cost overhead. However, by using the functional-unit fault-tolerant approach along with the traditional duplication approach, we can make a tradeoff between area overhead and performance degradation. In addition, the processor core of the ASIP has been made faulttolerant with lower area overhead than the traditional duplication method by putting a simpler application specific core as a redundant module for the main processor. Keeping only the data paths used by the running application in the redundant core enables us to reduce the redundancy cost with no performance overhead.

Keywords:

Embedded systems , Fault-tolerant systems , Standby sparing