A FGMOS-Based Four-Quadrant Current Multiplier with Reduced Power Dissipation

In this paper, we present a novel low-power, highspeedfour-quadrant analog multiplier which is based on a simplecurrent squarer circuit. The squarer circuit consists of a floatinggateMOS (FGMOS) transistor, operating in saturation regionand a resistor. The proposed multiplier has a balanced structurecomposed of four squarer cells and a simple current mirror. Thismultiplier also has a unique property of not using bias currentswhich results in greatly reduced power. For performanceevaluation, the design was simulated using HSPICE software in0.18 μm TSMC CMOS technology. Using ±0.5 V DC supplyvoltages, the simulation resulted in the maximum linearity errorof 0.8%, the -3dB bandwidth of 635 MHz, the Total HarmonicDistortion (THD) of 0.57% (at 1 MHz), and maximum and staticpower consumptions of 24 μW and 5.75 μW, respectively.Furthermore, to verify the robustness and reliability of theproposed work, Monte Carlo analysis was performed. For thisanalysis, 5% variations in channel width and length, gate oxidethickness and threshold voltage of all transistors and resistancevalues were considered.

Keywords:

four-quadrant multiplier , current squarer , saturation region , floating-gate MOS ,