A Novel Clustering Interconnection Architecture for Large-Scale Network-on-Chip

Driven by continuous scaling of Moore’s law, the core count on chip multiprocessors (CMPs) and system-on-chip are expected to increase tremendously in the near future. Therefore, connecting the different components of a CMP in a Network-on-Chip (NoC) in a scalable and efficient way becomes increasingly challenging. Some links are likely to be used more excessively than others, which can lead to unacceptable performance on the NoC. Transmitted packets inside a large NoC have long paths to reach their destinations. The long path increases latency, power consumption, and congestion, and decreases throughput. Existing NoC topologies are suitable only for small size NoCs. This paper describes a new topology for large-scale NoCs called RaMesh. RaMesh is suitable for large-scale NoCs that have up to thousands of IP cores. Experimental results show that the proposed topology and the accompanying routing algorithm have better performance than mesh and torus topologies for large-scale NoCs.

Keywords:

Network-on-Chip , Large-Scale NoC , NoC Topology , Clustering Architecture , Routing algorithm , Router , Switch