Design and Analysis of Power and Area Efficient with High speed VLSI Architectures for Communication Signal Processing Based on Multiplier Block using Compressors on FPGA

A methodology for VLSI realization of signal processing algorithms for wireless communications is presented that optimizes architecture for reduced power and area. When power is limited, optimal architecture represents a point on the best power-area tradeoff curve that is obtained by balancing the algorithms. The main theme of the paper is to design Compressor Based Low Power high speed and Area Efficient Multipliers on FPGA. More number of adders are required for the partial product addition. Special kind of adders are introduced which are capable of adding five/six/seven/eight/nine bits per decade with which we can reduce the number of adders and these special kind of adders are called as compressors. In order to develop higher order compressors, the combination of XOR gates and MUX circuits along with the binary counter property is contrasted with the conventional design. In this paper we present efficient implementation of multipliers with compressors on FPGA. When compared to carry propagate adders (CPA), high speed compressors provide fast critical path, independent of bit width with practically no area overhead. Design of such compressors will reduce the stage delays, transistor count and power delay product (PDP) and the results are verified in SPARTAN 3 FPGA. Architectural optimization is done which is also used for algorithm verification

Keywords:

Architecture , Design Methodology , FPGA , Multiplier , Carry propagate Adder , Compressor , counter