A Dynamic Double-edge-triggered D-type Flip-Flop
Publish place: Fifth International Conference on Quality Research in Electrical and Mechatronics Electrical Engineering
Publish Year: 1397
نوع سند: مقاله کنفرانسی
زبان: English
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شناسه ملی سند علمی:
ELEMECHCONF05_273
تاریخ نمایه سازی: 21 خرداد 1398
Abstract:
A dynamic negative-edge-triggered D-type flip-flop (D-NETFF) with four clocked transistors is developed based on the true single-phase clock (TSPC) dynamic technique. The performance of the D-NETFF is compared with that of a static master-slave D-type flip-flop in a 90nm CMOS technology based on SPICE simulations. Furthermore, the DNETFF is combined with its positive edge-triggered equivalent, D-PETFF in a single topology using a 2:1 multiplexer to develop a dynamic double-edge-triggered D-type flip-flop (DETFF). Operating with a 0.9-V power supply at a clock frequency of 16.7 GHz, the proposed DETFF exhibits an average Clock-to-Q delay of 25 psec and consumes 486 μW in a 20nm CMOS technology. Compared with common static latch-based flip-flops, dynamic TSPC flip-flops are faster, employ a smaller number of transistors and consume less power.
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Authors
Shahriar Jamasb
Department of Biomedical Engineering, Hamedan University of Technology, Hamedan, ۶۵۱۶۹-۱۳۷۳۳, Iran