Investigation of the Geometrical Effects on Nanoscale Filed Effect Diodes

In this paper, the previously proposed Modified Field Effect Diode (M-FED) has been more accurately studied and its current-voltage characteristics have been extracted numericallyby MINIMOS-NT device simulator. Simulations using this program provided the opportunity to study the effect of differentdevice parameters on the overall device performance. Our numerical results show the geometrical effects on the M-FED performance. Several parameters have to be scaled down suchas gate oxide thickness, channel length, the body thickness and the spacer length between two gates to achieve desirableelectrical characteristic. We demonstrate that a well-tempered device with a high switching response and lower energyconsumption can be achieved with a 30nm body thickness, 2nm gate oxide thickness, and 5nm spacer length

Keywords:

Modified field effect diode , Optimization , Gate delay time , Energy-delay product