A New 8-Transistors Floating Full-Adder Circuit

In this paper, a new high-speed full adder cell called Floating full adder has been proposed. This design offers a full adder with 8 transistors which its internal nodes are not directlyconnected to the ground. Simulations have been performed by Hspice software based on 90nm CMOS model, BSIM4 (level 54)version 4.4. Simulation results show that suggested circuit has maximum propagation delay equal to 33pS and average dissipation power of 87.53μW and PDP of 2.89fJ at 1GHz inputsignals frequency, which shows the circuit has low power dissipation at high speeds.

Keywords:

Floating full adder , low power , high speed