A 0.5V 200MHz offset trimmable latch comparator in standard 0.18um CMOS process

this paper presents a new high -speed ultra low -voltage dynamic latch comparator with rail -to-rail input range and an offset trimmig technique. Low voltage constraints especially sub-1V applications make the conventional comparator circuits inefficient to operate with high-speed rate. to overcome this issue a boosting technique has been utilized to increase the overdrive voltage of croaa coupled deveices and so speed -up the regeneration phase. the simulation results for the designed compator in standard 0.18um. CMOS process show that the comparator can detect 200uv input difference at 200 MHZ frequency while consumes 20.5uW in the latch and 8uW in the offset trimming blocks from a 0.5v supply.

Keywords:

dynamic comparator , latch comparator , low voltage , high speed sub volt , offset trimming