Implementation and Design of the 17- bit second order Delta –Sigma ADC on Spartan6

In modern world, electronics industry is moving more and more towards digitalization. Since everything in nature is in the analog form and in case any analog signals need to be digitally processed, they should be converted from analog to digital by an ADC converter. Then, after they are digitally processed, they should be converted into the analog form by DAC. Since there is an intense competition in the international markets over price, it can be argued that FPGA chips have very reasonable prices and are well-designed for all types of implementations. This was one reason for implementing the optimized model on FPGA. In this paper, The proposed structure was simulated in Matlab and the feedbacks of the coefficients and noise transmission function were obtained. Simulation results indicated that the proposed structure can be used to obtain a convertor with 110 dB signal to noise ratio and 17 bit accuracy. A 2nd Sigma Delta Modulator is the targets signal band of 20 k Hz for ham voice applications with an Oversampling Ratio of 512 and a sampling frequency of 20.48 M Hz. Finally, its execution on Spartan 6 FPGA kit

Keywords:

Sigma Delta ( ) , Analog-to-Digital Converters (ADC) , Field Programmable Gate Arrays (FPGA) ,