A Review on Soft Error-Tolerant Techniques in Different Levels of Digital Systems

Advances in technology and a reduction the size of transistors cause new problems for the design and manufacture of electronic chips. One of these problems is increasing the vulnerability of digital circuits against soft errors caused by the energetic particles, and thus, leads to reducing the reliability of digital circuits on a nanoscale. Continual scale-down of the transistor sizes leads to increasing the vulnerability and decreasing the reliability of digital systems.Therefor, providing new methods for reducing the soft error rate of digital systems becomes more crucial than ever. So far, some methods are provided to enhance reliability of digital systems against soft errors in different levels (transistor level, circuit level, architecture level and algorithm level). In this paper, we identified and classified some of the methods that are provided to reduce soft error rates in the digital systems.

Keywords:

Digital Systems , Reliability , Fault Tolerant , Transient Fault , Soft Error , Soft Error Rate (SER) , Error Detection , Error Recovery