New Domino Design for Robust High Fan-in Gates

High fan-in domino gates are used in the critical path of modern microprocessors to improve the performance, but the conventional domino logics suffer from leakage current and lower noise immunity, especially in sub-micron technologies. In this paper, a new circuit design for low leakage and noise immune high fan-in domino gates is proposed. The proposed circuit technique uses diode-footed transistor and current mirror to control PMOS keeper transistor. This results in reduction of the contention between the keeper transistor and pull down network from which other techniques suffer. Moreover, by using the stacking effect, leakage current is reduced and the performance of the current mirror is improved. High fan-in OR gates are simulated using a 07-nm CMOS predictive technology model (PTM) at a power supply of 7.0-V. Simulation results demonstrate that the proposed circuit exhibits about %72 less power consumption and nearly %2 fold improvement in noise immunity compared to the standard domino circuit.

Keywords:

domino logic , high fan-in gates , noise immunity , leakage current