A Frequency Compensation Technique for Two Stage OpAmps

A technique for compensation of two stage OpAmps is presented in this paper. The proposed technique is based on the removal of the first and the second non-dominant poles by left-half plane zeros. Besides miller compensation component, a very small compensation capacitor is needed which makes the simplicity and low area realization of the amplifier possible. The unity gain bandwidth of hundreds of megahertz and relatively low power consumption can be achieved for a two stage opamp, using this technique. Simulation results for the proposed amplifier in 180nm CMOS reveals a UGBW of 142MHz, DC gain of 63dB, and phase margin of 66 degrees for 0.5pF load capacitor.

Keywords:

Frequency Compensation , non-dominant Pole , OpAmp , Pole Location , Two-Stage , Zero Location.