An Ultra Efficient and Reliable TG-PTL Based Full Adder Cell

In this paper by using particular features of transmission gate (TG) and pass transistor logic (PTL) techniques a new full adder cell with 16 transistors proposed and investigated. Owing to used techniques, low number of transistors required which leads to low number of internal nodes and parasitic capacitances. As privileges of the proposed cell, ultra-low power consumption, high speed and performance and low energy dissipation based on small area occupation can be named. Extensive simulations such as power supply, frequency, load capacitance and temperature along with process variations applied. Accuracy and robustness of the proposed cell versus mentioned circumstances confirmed its ability for being used in next future generation of integrated circuits.

Keywords:

1-Bit Full Adder , Process Variation , Transmission Gate , Pass Transistor Logic