Reducing Quantum Cost for Reversible Realization of Densely-packed-decimal Converters

At present, the reduction of circuit design power is a prime research topic. The reversible computation satisfies the criteria of the power consumption reduction compared to the traditional logic design. Thereby, reversible computation is gaining much attention in recent decades. Two reversible design approaches of binary-coded-decimal (BCD) to densely-packed-decimal (DPD) converter (encoder) and two design approaches of DPD to BCD converter (decoder) are proposed in this paper. The designs are carried out through the appropriate selection of the gates and further proper organization of such gates with parallel implementation. The proposed design approaches offer a low quantum cost implementation compared to state-of-the-art design. The cost results analysis of reversible DPD encoder shows appreciable reduction by at least ~۲۳%, and that of decoder by at least ~۶۲% compared to the state-of-art design found in the literature. Furthermore, the structures are decomposed into the primitive-quantum-gates and compressed in compact form for delay calculation

Keywords:

Binary-coded-decimal , densely-packed-decimal , quantum cost , primitive-quantum-gates , delay