Design of High speed explicit pulsed Flip Flop in ۹۰ nm CMOS technology

Today, speed is an integral part of the industry, especially electronics and electronic devices. One of the most widely used tools in the field of electronics are flip-flops. Hence, in this paper, a fast explicit pulsed flip-flop is designed, simulated and proposed. The main idea is to modify the pulse generator circuit in the flip-flop to increase the speed, which was done by removing the two NOT gates from the Pulse generator circuit and the entire pulse generator circuit was resized. Pulse generator circuit in pulsed flip-flops is required for proper operation of flip-flops, for this reason, the main comparison was made on the new ۵-flip-flop pulse generator circuits in ۹۰nm CMOS technology. The simulation results using Hspice software showed the improvement in input-to-output delay and clock-to-output delay parameters and power delay product parameter (PDP), in which the proposed flip-flop showed a ۱۶.۳% reduction in clock to output delay and also a ۳۳.۳% reduction in clock to output PDP.

Keywords:

Flip-Flop , explicit , speed , pulsed , delay , PDP.