m alisafaee - department of electrical and computer engineering university of tehran
z navabi
s.m fakhraie

design of high -speed network switches and routers is normally limited by the memory bandwidth. In this paper we rpopose an architecture for network buffers which doubles the memory bandwidth for single-gueue network buffers. Here we use two parallel single -port memory devices to double the memory bandwidth. by using our architecture the overall memory appears as a dual-port memory from outside which can perform one read and one write operations simultaneously. the novelty of our solution is in introductionof a write policy which uniformly distributes the arriving packets between two memory piecess.

memory bandwidth,network buffers, high-speed switchesand routers