new methods to reduce energy and area in synchronous circuits following the decomposition stage

reducing energy consumption and area has been one of the prime objectives of digital circuit designers this paper intorduces a method to decompose the high level specification of Quasi delay insensitive QDI based asynchronous circuits then three methods are presented to reduce consumed energy and area after the decomposition stage. our experiments show that we gain reductions around 30% for energy and 20% for area.

Keywords:

synchronous , high level synthesis , optimization