Fully Differential Current Buffers Based on a Novel Common Mode Separation Technique

In this paper a novel common mode separation technique for implementing fully differential current buffers is introduced.  Using the proposed method two high CMRR (Common Mode Rejection Ratio) and high PSRR (Power Supply Rejection Ratio) fully differential current buffers in BIPOLAR and CMOS technologies are implemented.   Simulation results by HSPICE using ۰.۱۸μm TSMC process for CMOS based structures in ۱.۴V supply voltage and transistor models NUHFARRY and PUHFARRY for BJT based one in ۱.۶V supply voltage show CMRR of ۳۲.۹dB and ۳۳.۱dB for CMOS based and BJT based fully differential current buffers respectively. The proposed fully differential current buffers show PSRR- of ۱۱۴dB and ۱۱۶dB in CMOS and BIPOLAR technologies respectively while their PSRR+ are ۱۰۰dB and ۱۰۹dB respectively. The proposed common mode separation technique can also be arranged in partial positive feedback configuration to provide high current gain too. Simulation results of this configuration in CMOS technology, show current gain and CMRR of ۲۰.۸۶dB and ۵۳.۹۱dB respectively. The proposed method tends to be a fundamental technique in current mode signal processing capable to be much further improved and utilized.

Keywords:

Common Mode Separation Technique , Fully Differential Current Buffer , Fully Differential Operation , High CMRR Current Input Stage , High PSRR , Low Voltage Design