Shubham Tayal - Department of Electronics & Communication Engineering, Sree Dattha Institute of Engineering and Science, Telangana, India.
Pachimatla Samrat - Department of ECE, Ashoka Institute of Engineering & Technology, Hyderabad, Telangana, India.
Vadula Keerthi - Department of ECE, Ashoka Institute of Engineering & Technology, Hyderabad, Telangana, India.
Biswajit Jena - Department of ECE, Koneru Lakshmaiah Education Foundation, Amaravati nehi Vaddeswaram, India.
Karthik Rajendra - Department of Electronics and Communication Engineering, MLR Institute of Technology, Hyderabad, Telangana, India.

In this article, the high-k gate dielectric effect on the operation of complementary metal oxide semiconductor (CMOS) inverter build using conventional (CL) double-gate (DG) metal oxide semiconductor field effect transistor (MOSFET) and junctionless (JL) double-gate (DG) MOSFET has been explored. It is found that the improvement in inverter performance is more pronounced in CL-DG-MOSFET based CMOS inverter in comparison to JL-DG-MOSFET based CMOS inverter when SiO۲ is replaced by the high-k dielectric at gate oxide. The improvement in low noise margin (ΔNML), high noise margin (ΔNMH), gain (ΔA) & propagation delay (Δp < sub>d) is ۳.۱۹%, ۱.۶۴%, ۵.۲% & ۰.۹% respectively when SiO۲ is replaced by TiO۲ at gate oxide in case of CL-DG-MOSFET based CMOS inverter whereas it is ۱.۹۶%, ۱.۲۴%, ۳.۴% & ۱.۷۱% respectively in case of JL-DG-MOSFET based CMOS inverter. Consequently, the utilization of high-k dielectric as gate oxide is more advantageous in CL-DG-MOSFET devices for improved stability and gain of CMOS inverter.

CMOS Inverter, DG-MOSFET, Gate-Stack, High-k, Junctionless