Vimala Palanichamy - Associate Professor, Department of Electronics and Communication Engineering, Dayananda Sagar College of Engineering, Bangalore, India.
Netravathi Kulkarni - PG Scholar, Department of Electronics and Communication Engineering, Dayananda Sagar College of Engineering, Bangalore, India.
Arun Samuel Thankamony Sarasam - Associate Professor, Department of Electronics and Communication Engineering, National Engineering College, Kovilpatti, Tamilnadu, India.

In this paper, we proposed a ۲-D analytical model for electrical characteristics such as surface potential, electric field and drain current of Silicon-on-Insulator Tunnel Field Effect Transistor (SOI TFETs) with a SiO۲/High-k stacked gate-oxide structure. By using superposition principle with suitable boundary conditions, the Poisson’s equation has been solved to model the channel region potential. The modeled channel potential is to calculate both vertical and lateral electric field.  ۲-D Kane’s model is used to calculate the drain current of TFET and the expression is taken out by analytically integrating the band-to-band tunneling generation rate over the thickness of channel region. The device is modeled in variation with different device parameters like channel length (LCH), dielectric thickness (tox), silicon thickness (tsi) and input voltage (Vds and Vgs). Also, the comparison of SiO۲ and stacked high k dielectric TFET is obtained. It has been found from the presented results that the hetero-dielectric stacked TFET structure provides ON current ۱۰-۶A/um. However, SiO۲ dielectric structure provides the ON current of ۱۰-۸A/um. The proposed model is validated by comparing it with Technology Computer-Aided Design (TCAD) simulation results obtained by using SILVACO ATLAS device simulation software.

Analytical Modeling, High-k Dielectric, Poisson’s Equation, Superposition Principle, Tunnel FET (TFET)