A fast wallace-based parallel multiplier in quantum-dot cellular automata

Physical limitations of Complementary Metal-Oxide-Semiconductors (CMOS) technology at nanoscale and high cost of lithography have provided the platform for creating Quantum-dot Cellular Automata (QCA)-based hardware. The QCA is a new technology that promises smaller, cheaper and faster electronic circuits, and has been regarded as an effective solution for scalability problems in CMOS technology. Therefore, it is possible to generalize QCA to all digital components. Multipliers are considered as one of the most important building blocks of computational circuits in digital processing systems. The traditional design of multipliers results in wasting the resources and increasing computational time. This paper presents an effective implementation of QCA parallel multiplier based on Wallace tree. It is able to significantly reduce the occupied area by reducing the number of QCA cells and therefore increases the speed of multiplying operation. The proposed QCA multiplier is simulated by QCADesigner۲.۰.۳ software. The simulation results confirm that the proposed QCA multiplier works well and can be used in high performance circuits in QCA technology. Moreover, the proposed QCA multiplier has less complexity and occupied area compared to other QCA multiplier designs.

Keywords:

Full adder , Half adder , Multiplier , nanotechnology , Quantum-dot cellular Automata , Wallace tree