A Reusable and Scalable VHDL Model of a Scheduling Algorithm in Input-Queued Switches

Crossbar switches are frequently used as the internal switching fabric of high performance network switches and routers. However, an intelligent scheduler is needed to configure the crossbar fairly and with high utilization. In this paper, we describe a hardware design and implementation of one of the weighted scheduling algorithms for configuring crossbars in input-queued switches that supports virtual output queues. The main feature of the developed VHDL model is being reusable and configurable for bigger switches. The proposed hardware design was synthesized for a 16×16 switch scheduler and programmed in a FPGA

Keywords:

High-Speed Router , Input-queue switches , Scheduling Algorithm