MULTI-LEVEL LOGIC SYNTHESIS USING HYBRID PASS LOGIC AND CMOS TOPOLOGIES

For many digital designs, implementation in Pass Transistor Logic (PTL) is superior to conventional static CMOS in terms of chip area, delay and power dissipation. However, due to the lack of a standard implementation methodology and very limited commercial tool support, PTL has not yet achieved its full potential. This paper describes the development of an automated logic synthesis tool, which has the capability of utilizing a new multi-level mapping algorithm to realize logic functions into PTL. A subset of MCNC91’ benchmark circuits were used to evaluate the tool, and the results are compared to those generated by Design Analyzer, a commercial tool from Synopsys Inc. An improvement of an average of 27% in powerdelay product was achieved when using our cell library, which is based on the TSMC’s 0.18μ process provided through the Canadian Microelectronics Corporation (CMC

Keywords:

Pass Transistor Logic , synthesis , BDD , low power