DELAY AND POWER ESTIMATION OF CMOS INVERTERS

In this paper, a new simple yet accurate model for determining the delay and the power consumption of a state of the art static CMOS inverter is introduced. This analytical model uses the modified version of n-th power law MOSFET model which is appropriate for short channel devices. The short-circuit current, which is used in the calculation of the power consumption, is modeled by a piecewise linear interpolation scheme. The short-circuit current used for the interpolation is obtained from the HSPICE simulation with complete level 49 model parameters including all capacitances. For the evaluation of the inverter delay, an accurate model is presented. Although the proposed model is much simpler compared to the previously reported models, it has a very good accuracy which is confirmed with HSPICE simulations