Anahita Bagheri - Faculty of ECE, Kerman Graduate University of Technology, Iran
Nasser Masoumi - Advanced VLSI Lab., School of ECE, College of Eng., University of Tehran, Iran

Most of the power consumption and chip area in FPGAs mainly depend on the routing properties such as the architecture, interconnects, and resources. Many researches have been conducted on routing resources to reduce the power and area, but rarely the impact of wire segmentation structure, as a part of routing resource, have been studied in details. In this paper based on extensive simulations, we extract the wire lengths of the most probability usage, and then an optimum combination of the wire segmentation, called 12HL, is chosen. Subsequently, we propose a methodology based on the stochastic process and probability study to estimate the optimum ratio of the wires in the 12HL combination. In this investigation, rather an inclusive group of benchmark circuits have been implemented in Spartan-3 in 32nm technology. We show that, using the proposed ratios for the wire segmentation model leads to a reduction of more than 40% of the power, 20% of the area, 38% of the power × net delay, 53% of the power × net delay × area, and 27% of the minimum channel width.

FPGA, wire segmentation, wire length probability, routing resources, interconnect