pedram Payandehnia - Electrical and Computer Engineering Department, University of Tehran, Tehran, Iran
Hamidreza Maghami
Samad Sheikhaei
Aliazam Abbasfar

In this paper, a high speed latch architecture is proposed. This latch is based on a modified CML architecture, in which the tail current source is removed. To further increase the speed, shunt peaking is used. This technique can be implemented using passive or active inductors. Active inductors require smaller on-chip implementation area, but impose some drawbacks such as nonlinearity and noise. Fortunately, these drawbacks can be tolerated in a shunt peaking CML latch. In addition to cost effective implementation, using active inductors in the modified CML latch allows for optimizing the inductance values independently for the track and evaluation phases. This is not possible with passive inductors or common CML latches. Simulations predict that the active inductor loads increase the speed by more than 50% compared to resistive loads, when simulated in 0.18μm CMOS technology with 1.8V supply

active inductor, current mode logic (CML) latch