FPGA Implementation of JPEG-LS Compression Algorithm for Real Time Applications

This paper presents some propositions to reduce consuming memory and increase operational frequency of hardware implementation of JPEG-LS algorithm for real time applications. Byenhancement in the algorithm and using fast divider, memory has been reduced by 24%. Also, considering the proposed non-stallingpipeline architecture by using forwarding technique to avoid hazards, circuit frequency has increased to 155.2MHz and any512x512 pixel image can be compressed in less than 1700us at these frequency and architecture. Compressor architecture was described by VerilogHDL and implemented on ALTERA Stratix II FPGA

Keywords:

JPEG-LS , Memory , Pipeline , Forwarding , FPGA