Mohammad Honarparvar - Sahand University of Technology
Esmail Najafi Aghdam - Sahand University of Technology

Dual mode high performance reconfigurable continuous time delta sigma modulator with concentration on reducing the active blocks and power saving is presented in thisarticle. The modulator makes use of a low distortion suppression topology which is suitable for wide band applications and a NoiseShaping Enhancement (NSE) technique for increasing the performance of the modulator. A None Return to Zero (NRZ) DACs pulse shaping are selected to decrease clock jittersensitivity and Excess Loop Delay (ELD) compensation is considered to increase the system stability. Also several noneidealities have been considered in this design. In device level, gm over ID method is opted for designing the modulator analoguecells. The modulator achieves 85/90 dB SNDR within 0.2/2 MHz bandwidth and consumes 3.4/5 mW for GSM and WCDMA standards respectively

Delta sigma Modulator, Reconfigurable, Multi Mode,gm over ID