A Novel ۳D Mesh-Based NoC Architecture for Performance Improvement

Applying semiconductor technology, network-on-chips (NoCs) are designed on silicon chips to expand on-chip communications. Three-dimensional (۳D) mesh-based architecture is also known as a basic NoC architecture characterized by better energy consumption and latency compared with two-dimensional (۲D) ones.  Recently developed architectures are based on regular mesh. However, there are serious drawbacks in NoC architectures including high power consumption, energy consumption, and latency. Therefore, making an improvement in topology diameter would overcome these shortcomings. Accordingly, a new ۳D mesh-based NoC architecture is proposed in the present study utilizing the star node, consisting of a new ۳D topology with small diameter and new deadlock-free routing. The diameter of this architecture is then compared with its counterparts. Afterwards, the scalable universal matrix multiplication algorithm (SUMMA) is implemented in the proposed architecture. The results indicate a smaller network diameter, lower energy consumption (۳۲%), less network latency (۸.۶%), as well as enhancement in throughput average (۱۳.۶%). The proposed matrix multiplication algorithm also implies improvement in the cost of the proposed architecture in comparison with its counterparts.

Keywords:

Communication , networks Architecture , Topology , Network-on-Chip , System-on-chip , Routing Protocols , Performance Evaluation , Multiplication Algorithm , Latency , Energy improvement , diameter