FIR and folded IIR filter designs for speech processing in hearing AID

The present trend of low power and area has led to the design of many efficient algorithms for speech processing in portable devices.  In biomedical applications like hearing aid, high performance is not the key area of interest. Area and power also play a major role. There are many factors that affect market penetration. So, the system can run as slow as possible to trade speed for power and area. An area-efficient folded IIR filter is designed. The folded architecture uses the concept of time multiplexing and it has only one multiplier and one adder to perform all the operations. Thus, the area is reduced, and this filter is converted into an IP. The area and resource utilization of the folded IIR filter is compared with the normal IIR filter design. AFIR filter is also designed and converted into an IP. This FIR IP is used in the block design to process a corrupted audio signal. Zed board is a part of Xilinx zynq -۷۰۰۰ All Programmable SoC. It consists of a processing system and programming logic. The filter design is implemented in the programming logic part. The design is synthesized and the bitstream is generated. The generated bitstream along with the hardware is exported to SDK where the corrupted audio signal is processed on zed board.

Keywords:

Low power , IP , multiplexing , SOC , Processing system , Programming logic