Optimized Hardware Acceleration Design for Keccak Hash Function

Due to the increased popularity of cryptocurrency and especially low cost and high-performance hardware implementation of the related algorithms, this paper intends to investigate the related solutions. Keccak algorithm as one of the main important blocks of Lyra۲REv۲ algorithm which is a popular ASIC resistant chain algorithm is the goal of this research. FPGAs are low risk, cost efficient hardware for implementing the ASIC resistance hashing algorithms. In this paper an optimized SOC implementation of Keccak algorithm is studied. Different methods considering challenges of hardware design including power, efficiency and resource utilization are take into account. The final design achieves the clock frequency and throughput of ۳۳۳.۳۳ MHz and ۶.۸ Gbps respectively.

Keywords:

Keccak , hash function , cryptocurrency , SOC.