ASIC Implementation of Chained Cryptographic Hash functions

Due to the increasing popularity of chaincryptography algorithms, this paper focuses on theimplementation of Skein and Keccak cryptographic hashalgorithms, which are among the popular algorithms usedin chain cryptography algorithms. To implement theASIC design of the desired algorithms the specific designchallenges should be considered. Also, for the purpose ofcomparison, Zynq parts (including both FPGA and ARM)were considered for SOC design of these algorithms. TheZC۷۰۶ board is considered and selected as one of thefamous evaluation boards in Vivado software for SOCimplementation. ASIC design with ۴۵nm CMOStechnology is done in this paper. Design-vision andencounter tools are used to perform the synthesisoperation and extract the layout of the desired algorithm,respectively. In the ASIC design, the clock frequency ofSkein and Keccak is ۱۶۱.۲ and ۴۰۰ MHz, respectively.The reported area from the design-vision tool is ۲۱۰,۰۰۰and ۶۳,۰۰۰ (μm)۲ for the designs. The total powerconsumption of designs with ۴۵ nm CMOS technologyfor Keccak and Skein algorithms is ۲۸.۰۳ and ۳۹.۷ mW,respectively. In the SOC implementation, the clockfrequency for Skein and Keccak algorithms are ۱۴۲ MHzand ۳۳۳ MHz, respectively. Total power consumption is۰.۸۳۷ W @ ۱۴۲MHz for Skein and ۲.۴۹۲ W @ ۳۳۳MHzfor Keccak algorithm.

Keywords:

Keccak , Skein , hash function , cryptocurrency , SOC , ASIC , Zynq.