Performance Analysis of High Speed Radix-۴ Booth Encoders in CMOS Technology

This review paper deals with performance analysis of the published works for circuit level realization of radix-۴ Booth encoder/decoders. Starting from general concept of Booth algorithm in brief form, the conventional truth table is discussed. Subsequently, the modifications which led to the circuit level implementations along with the complete and comparative analysis for the selected works, is provided. Simulations using HSPICE for TSMC ۰.۱۸µm CMOS technology and ۱.۸V power supply have been performed for comparing these works. Considering the required optimizations applied to the mentioned works, it can be deduced that ۱.۵ XOR gate level delay is reachable for radix-۴ Booth encoding scheme while the output waveforms are free of any glitches. The optimized version of Booth encoder has been embedded in a ۱۶x۱۶ bit parallel multiplier in which, the measured latency after post layout simulations is ۱۹۹۲ps; which demonstrates the high potential of chosen radix-۴ Booth encoding scheme for utilization in high speed parallel multipliers.

Keywords:

Parallel multiplier , Booth Encoder , Radix-۴ , High speed