Navneet Kaur - I. K. Gujral Punjab Technical University, Jalandhar, Punjab, India
Munish Rattan - Guru Nanak Dev Engineering College, Ludhiana, Punjab, India
Sandeep Gill - Guru Nanak Dev Engineering College, Ludhiana, Punjab, India

FinFETs are the emerging ۳D-transistor structures due to strong electrostatic control of active channel by gate from more than one side which was not possible in conventional transistor. FinFET structures with rectangular and trapezoidal shape have been excessively analyzed in literature. In this work, FinFET with Broadwell-Y shape proposed by Intel, has been designed and simulated in Technology Computer Aided Design (TCAD). The performance of the designed device was optimized using Moth Flame Optimization (MFO) after the network was trained through Artificial Neural Network (ANN). Results obtained from MATLAB were in close agreement with those obtained from TCAD simulations. Output parameters like leakage current (IOFF) of ۲.۴۰۷e-۱۲, On-Off current ratio (ION/IOFF) of ۴.۵e۰۶, Subthreshold Swing (SS) of ۶۵.۴mV/dec and Drain Induced Barrier Lowering (DIBL) of ۳۷.۹mV/V were obtained after optimization. Short channel effects are improved for ۲۰nm gate length as SS is close to ideal value ۶۰mV/dec and DIBL is below ۱۰۰mV/V which makes this designed structure a good option for nanoscale applications.

FinFET, Moth-Flame Optimization (MFO), Artificial Neural Network (ANN), Drain Induced Barrier Lowering (DIBL), Subthreshold Swing (SS), Leakage Current, TCAD, MATLAB, Fin height, Gate length