Leila Jahan panah - Department of Electrical Engineering, Mahshahr Branch, Islamic Azad University, Mahshahr, Iran
Seyed Ali Sadatnoori - Department of electrical Engineering, Shoushtar branch, Islamic Azad University, Shoushtar, Iran
Iman Chaharmahali - Department of Electrical Engineering, Andimeshk Branch, Islamic Azad University, Andimeshk, Iran

Digital Sigma Delta Modulator architecture is widely used in fractional frequency synthesizers. A frequency synthesizer is a major component of wireless communication systems. The output of the frequency synthesizer system is locked based on the phase lock loop at a specific reference frequency. In this case, the output frequency is the same as the oscillator frequency of the VCO. The main advantage of digital sigma delta modulator with multi-layer structure is its ability to be implemented as a pipeline. This method will reduce the delay and increase the sampling frequency. In this paper, a digital sigma delta modulator of separate lines is designed by pipeline method and its power spectral density is plotted. This method increases the speed of the modulator and reduces the hardware consumption.

Digital Sigma Delta Modulator, Pipeline Method, Hardware Consumption, Speed