Soorena Zohoori
Mehdi Dolatshahi

In this paper, a one-bit ultra-low-power full adder cell using GDI structure is proposed. Main objective of this design is not only providing low power consumption, but also providing full swing outputs. In this paper, combination of different logics and stacking technique are used to provide an ultra-low power cell. Also, by using stacked inverters after each function, full swing characteristic for the cell is obtained. These characteristics are obtained in cost of more occupied chip area and higher delay.  In order to verify the performance of the proposed cell, simulations are done in HSPICE using ۹۰nm CMOS technology library. Beside Noise immunity, power consumption is also analyzed under different load conditions, different supply voltages and different temperatures. Although delay of the circuit is increased, results show a tremendous reduction in power consumption and an improved power-delay-product for the proposed full adder cell.

ultra-low-power, GDI, Full adder