Design Low Power Carry Save Adder Based On 4*4 Multiplier

Our objective in this paper is to select algorithm to minimize the power consumption and area we also discuss way to configure multiplier 4*4 to sum vector in a carry save adder(csa) tree. we evaluate not,nand,xor and nor gate and using Hspice implementation using 0.35um cmos technology, the result of this algorithm advantageously applied to low power device. We reduce the number of transitions csa trees that are common in large multiplier. In transistor level circuit simulations indicate 20-30% power reduction with no increase in delay

Keywords:

Carry Save Adder , Low Power Multiplier , Critical Path , VlSI Design