Employing Different Modes of Power Gating on ARM Processors by 16nm FinFET

In this paper a power gating approach is reintroduced and applied to different alpha processor building block in the RTL level to reduce the static power of theentire processor. Different modes of power gating based on their contribution on leakage saving and overhead are introduced and their leakage saving are compared. The sleep transistor is a NFET which has a little wake-up time overhead on the design. Static power of the whole processor isreduced with desirable performance by use of optimization algorithm in distributing the sleep modes over the digital blocks. Each block is shut down in the design when the application call to that block is lowered by processor’s controller. The power reduction methods in more complexprocessor as Gap, Vortex, SAYEH, Mgrid and Swim is compared to their conventional performance by inspecting the penalties of wake-up’s energy and delay. The average wake-up time and energy overhead of the multi-mode power gating are 2.9% and 2.2% respectively. At the expense of these overhead the average power of an ARM processor is reduced by 18.2%.

Keywords:

Power gating , wake up energy and time , PVT corners , power and delay trade-off