A Low Power, Variability Resilient 9T-SRAM Cell Operating Stable in Sub and Near-Threshold Regions Using 16nm CMOS technology

this paper describes the characteristics of a new structure of SRAM cell which works quite well in three different levels of voltage including sub-threshold, nearthreshold and strong inversion operating regions of MOSFETs. Use of a series transistor with the cell and read paths simultaneously results in huge power reduction in the cell and make it viable to be used in lower level of supply voltage. To reduce the power, series transistor is forced to offmode by a hold signal and can increase the virtual ground of the back-to-back inverter and read paths. Lowering theleakage of the cell and read path can increase both the staticnoise margin (SNM) and the write margin while keeping the cell value stable even with lower supply voltage. To show theappealing read SNM and write margin, it is compared with other topologies in the same or even lower powerconsumption. Comparison of ST10T (LP10T) with the cellshows 77% (31%) improvement in read SNM and 100%(3.7%) reduction in leakage of the cell. The simulations are done by HSPICE 2011 using Berkeley predictive technology model (BPTM) for 16nm CMOS.

Keywords:

SRAM , SNM , Subthreshold , Low Power , CMOS