Design and optimization of a CMOS comparator using genetic algorithm
عنوان مقاله: Design and optimization of a CMOS comparator using genetic algorithm
شناسه ملی مقاله: NCNIEE02_319
منتشر شده در دومین کنفرانس ملی ایده های نو در مهندسی برق در سال 1392
شناسه ملی مقاله: NCNIEE02_319
منتشر شده در دومین کنفرانس ملی ایده های نو در مهندسی برق در سال 1392
مشخصات نویسندگان مقاله:
Mehdi Dolatshahi - Assistant professor, Electrical Engineering Department, Najafabad Branch, Islamic Azad University, Isfahan, Iran
Arvin Hojjat Panah Montazeri - Electrical Engineering Department, Najafabad Branch, Islamic Azad University, Isfahan, Iran
venous moslemi - Department of engineering and built environment, University of Kebangsaan, Kualalumpur, Malaysia
خلاصه مقاله:
Mehdi Dolatshahi - Assistant professor, Electrical Engineering Department, Najafabad Branch, Islamic Azad University, Isfahan, Iran
Arvin Hojjat Panah Montazeri - Electrical Engineering Department, Najafabad Branch, Islamic Azad University, Isfahan, Iran
venous moslemi - Department of engineering and built environment, University of Kebangsaan, Kualalumpur, Malaysia
This paper presents the design and optimization of a low-power regenerative latched CMOS comparator, based on genetic algorithm (GA). In this paper, the required values oftransistors dimensions (W, L) calculated using genetic algorithm in MATLAB while the circuit is simulated in HSPICEusing 0.18μm CMOS technology parameters
کلمات کلیدی: CMOS comparator, Genetic Algorithm, VLSI
صفحه اختصاصی مقاله و دریافت فایل کامل: https://civilica.com/doc/233814/