Behnam Ghavami - GomputerE ngi n eeringD epartmentA, mi rkabri Un iversityo f Techn ology (TehranP olytechntcl۴۲۴H afezA ve,T ehran۱ ۵۷۸۵,lr an
Atabak Mahram - GomputerE ngi n eeringD epartmentA, mi rkabri Un iversityo f Techn ology (TehranP olytechntcl۴۲۴H afezA ve,T ehran۱ ۵۷۸۵,lr an
Hossein Pedram - GomputerE ngi n eeringD epartmentA, mi rkabri Un iversityo f Techn ology (TehranP olytechntcl۴۲۴H afezA ve,T ehran۱ ۵۷۸۵,lr an

QDI Dual-rail asynchronous circuits, if implemented carefully balanced, have nahral and effrcient resistance to side-channel attacks in cryptography applications. Due to hardware redmdancy in previous balanced gate desigrs, there are many faults which can make them imbalanced without causing logical errors. Therefore, traditional logical testing methods are unable to test and verifr if a gate is completely fault-fiee and hence balanced. This wlnerability opens the possibility of new methods of attacks, based on a combination of fault and power attacks in cryptographic applications. In this paper we present an asynchronous approach to hardware implementation of DESI crlptography algorithm that countermeasures against this new multiple side+hannel attrack.

Asyncbronous Circuiq Cryptography, QDI, Side-channel attack, DES algorithm