A novel Fault tolerance routing algorithm in through silicon vias (TSV) in three dimensional networks on chip

NOC is introduced as a useful and effective solution for omitting busses and making a profitinterface for processors connections. With degradation in transistors dimensions andcomplication of circuits, 3D chips are presented as a profit solution in circuits designing.Otherwise this dimension degradation increases probability of faults. So fault tolerance is one ofthe most important challenges in digital circuits designing. In this paper a routing algorithm(SM) is suggested with purpose of incrementing fault tolerance in network links especially invertical ones. The presented routing algorithm with use of a through layer routing table and towfault tables for vertical (TSV) and horizontal links in every layer has a significant improvementin performance parameters like delay, reliability and throughput instead of a small increment inoccupied space in every switch. The result of simulation on a 7×7×7 and 4×4×4 3D mesh NOCshows that with injection of 12% faults in network links for real and synthetic traffic work load,the network latency decreased respectively 42/67% and 46/61%. Also the network reliabilityimprovement is 16/9%.

Keywords:

3D-NOC , Fault tolerance routing algorithm , TSV , SOC , Deflection routing algorithm