An Implementation of Packet Switch Core on FPGA

This paper presents a hardware implementation of a high-performance switch core. It routes incoming data packets to proper output ports according to the destination field in the packet header. The Switch cores are key switching element in routers and other network equipment. Flexibility is the most significant feature of this implementation. FPGA design methodology let this implementation can be modified to meet various customer requirements in a short time and at low cost.The switch has been implemented only on a single chip (XCE4VFX60 from Xilinx) completely. The FPGA design flow is based on Xilinx Foundation ISE environment for synthesis and mapping onto the target device. This switch core can handle up to 100Gbps traffic with eight incoming ports and eight outgoing ports.

Keywords:

FPGA , Configurable System , Switch Core , Shared Memory , Barrel Shifter