Sarang Kazeminia - Microelectronics Research Laboratory, Urmia University, Urmia, West Azerbaijan, Iran
Khayrollah Hadidi - Microelectronics Research Laboratory, Urmia University, Urmia, West Azerbaijan, Iran
Abdollah Khoei - Microelectronics Research Laboratory, Urmia University, Urmia, West Azerbaijan, Iran

In this paper, a 16-phases 20MHz to 110MHz low jitter delay locked loop, DLL, is proposed in a 0.35μm CMOS process.A sensitive open loop phase detector, PD, is introduced based on a novel idea to simply detect small phase differencesbetween reference clock and generated delayed signals. High sensitivity, besides the simplicity reduces the dead zone ofPD and gives a better jitter on output generated clock signals, consequently. A new strategy of common mode setting isutilized on differential delay elements which no longer introduce extra parasitics on output nodes and brings the dutycycle of generated clock signals near to 50 percent. Also, small amplitude differential clock is carefully transferred insidethe circuit to considerably suppress the noise effect of supply voltage. Post-Layout simulation results confirm the RMSjitter of less than 6.7ps at 20MHz and 2ps at 100MHz input clock frequency when the 3.3Volts supply voltage is subjectto 75mVolts peak-to-peak noise disturbances. Total power consumption reaches from 7.5mW to 16.5mW when theoperating frequency increases from 20MHz to 100MHz. The proposed low-jitter DLL can be implemented in small activearea, around 380μm×210μm including the clock generation circuit, which is proper to be repeatedly used inside the chip.

Delay Locked Loop; Clock Generation; Low-Jitter Clock Distribution; Wide-Range DLL; Low-Jitter DLL