Power reduction in digital VLSI circuits

The increased use of Portable electronics devices such as cellular phones, notebook and computers has made power dissipation an important design metric in modern microelectronics. Portable devices that operate using a battery have limited energy supplies and thus have lifetime that are constrained by their power consumption. Even ICs in systems that are plugged into a continuous power supply are becoming power constrained due to the difficulty of dissipating heat that results from consuming power on a chip with many tightly packed transistor. Our objective is to reduce power dissipation in digital CMOS VLSI circuits.later; we will compare all the optimal methods which can reduce maximum power dissipation among all and with fewer limitations. We have used Galaxy Custom Designer a tool of Synopsys and SPICE coding to find out delay, power, energy and leakage charge with the various design styles like CMOS, Pass transistor, DCVS (Differential cascade voltage switch logic circuit), Dynamic, DCVS-PG. We had computed the delay, power, energy and power leakage and compared amongst these design styles to conclude which design style would work for the specific requirement

Keywords:

VLSI , power reduction , design methodology for VLSI circuits , CMOS Implementation , power and delay of CMOS circuit