Design of New High-Performance Full Adder Using Hybrid-CMOS Logic Style for High-Speed Applications
عنوان مقاله: Design of New High-Performance Full Adder Using Hybrid-CMOS Logic Style for High-Speed Applications
شناسه ملی مقاله: COMCONF01_292
منتشر شده در کنفرانس بین المللی یافته های نوین پژوهشی درمهندسی برق و علوم کامپیوتر در سال 1394
شناسه ملی مقاله: COMCONF01_292
منتشر شده در کنفرانس بین المللی یافته های نوین پژوهشی درمهندسی برق و علوم کامپیوتر در سال 1394
مشخصات نویسندگان مقاله:
Milad Jalalian Abbasi Morad - Department of Electrical Engineering, Imam Reza International University, Mashhad, Iran
Seyyed Reza Talebiyan - Department of Electrical Engineering, Imam Reza International University, Mashhad, Iran
Ebrahim Pakniyat - Department of Electrical Engineering, Imam Reza International University, Mashhad, Iran
خلاصه مقاله:
Milad Jalalian Abbasi Morad - Department of Electrical Engineering, Imam Reza International University, Mashhad, Iran
Seyyed Reza Talebiyan - Department of Electrical Engineering, Imam Reza International University, Mashhad, Iran
Ebrahim Pakniyat - Department of Electrical Engineering, Imam Reza International University, Mashhad, Iran
This paper, presents a new design for 1-bit full adder cell using hybrid-CMOS logic style. Using a novel structure for implementation of the proposed full adder caused it has better performance in terms of propagation delay and power-delay product (PDP) compared to its counterparts. According to the simulation results, the propagation delay of the proposed full adder is 22.8% less than the propagation delay of next fastest full adder, and the power-delay product of the proposed full adder is 22.7% less than the next best PDP. HSpice simulations using 65nm technology with a power supply of 1.2V was utilized to evaluate the performance of the circuits
کلمات کلیدی: full adder, high-performance, high-speed, hybrid-CMOS, propagation delay
صفحه اختصاصی مقاله و دریافت فایل کامل: https://civilica.com/doc/404393/