A Novel Method for Transistor Sizing in Digital Circuits by Artificial Intelligence

In this paper a new optimization method is proposed for transistor sizing of VLSI digital circuits based on artificial intelligence. The optimized dimensions are especially conducted for minimizing power dissipation (dynamic and static power) and delay. In order to verify the efficiency of the proposed method, transistor’s dimensions of four well-known full-adder circuits in different frequencies and voltage levels are optimized and their results are compared to the previously reported results. Simulation results of HSpice provided in TSMC 0.18μm technology, show considerable improvement of power delay product (PDP) reduction. The results promise a strong impact since full-adders are the basic block in the most VLSI circuits

Keywords:

Transistor Sizing , Artificial Intelligence , Digital Circuits , Optimization