A Comparative Study of VHDL Implementation of FT-2D-cGA and FT-3D-cGA on Different Benchmarks

This paper presents the VHDL implementation of fault tolerant cellular genetic algorithm. The goal of paper is to harden the hardware implementation of the cGA against single error upset (SEU), when affecting the fitness registers in the target hardware. The proposed approach consists of two phases; Error monitoring and error recovery. Using innovative connectivity between processing elements and efficient correction policy, the PEs will prohibit spreading the faulty evaluated individual in the population. In the experiments, three metrics and four test functions are used to show the performance of the proposed structures. Two structures (2D and 3D) of proposed FT-cGAs are set to optimize various test functions. The experimental results illustrate the robustness of the proposed system. An outstanding outcome was that the implemented fault tolerant algorithm was able to reach the optimal solution when at least one processing element is healthy in population.

Keywords:

Fault Tolerance , Cellular Genetic Algorithm , FT-2D-cGA , FT-3D-cGA , Processing Element , Single Error Upset