Ghadami - Urmia University
Hadidi - Urmia University
Khoei - Urmia University

This paper describes the PLL based clock and data recovery circuit at 1.25 Gb/s. It consists of two loops to obtain low output jitter and increasing the acquisition range of the PLL. In this paper a half rate phase detector is presented and for reducing jitter generation in CDR circuit a novel voltage controlled oscillator is also introduced that works at half the data rate. The power dissipation is 25.5 mw from 3.3V supply and the circuit area is 0.24 mm2. The circuit exhibits an rms jitter of 10.7 ps and peak to peak jitter 30 ps in recovered clock.

Clock and data recovery, half rate, PLL, voltage controlled oscillator, phase noise